In general, there are various types of semiconductor memory devices such as Random Access Memory (RAM) and Read Only Memory (ROM). When power supply is disconnected, information stored in Random Access Memory (RAM) is lost, whereas information stored in Read Only Memory (ROM) is maintained. Therefore, the ROM is called a non-volatile memory device. An Electrically Erasable and Programmable Read Only Memory (EEPROM) device is a kind of a non-volatile memory device on which data can be electrically erased and programmed.
FIG. 1 is a cross-sectional view of an EEPROM device 8 according to the Background Art, that includes a memory transistor (MTR) and a corresponding selection transistor (STR). Referring to FIG. 1, a memory gate oxide layer 12 and a tunneling oxide layer 14 are formed on a semiconductor substrate 10. The thickness of the tunneling oxide layer 14 is thinner than that of the memory gate oxide layer 12. A floating gate 16 is formed on the memory gate oxide layer 12 and the tunneling oxide layer 14. Also, an insulating layer 18 and a control gate 20 are sequentially formed on the floating gate 16.
In the semiconductor substrate 10, a source region 22 is formed to be aligned with respect to sides of the floating gate 16 and the control gate layer 18. Viewing the memory transistor MTR as having a right half and a left half, a floating junction region 24 is formed under the right half of the MTR, and consequently is underneath the tunneling oxide layer 14. The source region 22 and the floating junction region 24 are N+ regions when the semiconductor substrate 10 is a P-type silicon substrate. The tunneling oxide layer 14, the floating gate 16, the insulating layer 18, the control gate 20, the source region 22, and the floating junction region 24 constitute the memory transistor MTR.
Being separated from the memory transistor MTR, a selection gate oxide layer 26 is formed on the semiconductor substrate 10. A gate 34, which includes a first conductive layer pattern 28, an insulating layer pattern 30, and a second conductive layer pattern 32, is formed on the selection gate oxide layer 26. A drain region 36 is formed under the right side of the gate 34. The drain region 36 is connected to a bit line (not shown). The drain region 36 is an N+ region when the semiconductor substrate 10 is a P-type silicon substrate. The selection gate oxide layer 26, the gate 34, the floating junction region 24, and the drain region 36 constitute the selection transistor STR.
Such a structure of the Background Art EEPROM device 8 causes a difference between voltages applied to the control gate 20 and the floating junction region 24 and thus makes Fowler-Nordheim (F-N) current flow through the tunneling oxide layer 14. Therefore, a memory cell of the EEPROM device 8 is erased or programmed by injecting electrons into or discharging electrons from the floating gate 16. In detail, implantation of electrons into the floating gate 16 causes erasure of the cell and discharge of electrons from the floating gate 16 causes programming of the cell.
An operating voltage used for the programming and erasure of the cell is determined by a coupling ratio, i.e., the extent that a voltage applied to the control gate 20 is applied to the floating gate 16. The coupling ratio is required to be increased to reduce the operating voltage. However, as the size of a cell of the EEPROM device 8 becomes smaller, a capacitance value between the floating gate 16 and the control gate 20 becomes reduced and the coupling ratio also decreases.
In the Background Art, it is known to increase the coupling ratio by reducing the thickness of an insulating layer between the floating gate 16 and the control gate 20 so as to increase a capacitance value therebetween, or reducing the size of the tunneling oxide layer 14. However, there is a limitation in lowering the thickness of the insulating layer 18 because it may result in charge loss. Also, there is a limitation in reducing the size of the tunneling oxide layer 14 using a patterning process. As a worst case scenario, a reduction in the size of the tunneling oxide layer 14 reduces the reliability of a memory device.